diff options
Diffstat (limited to 'libhw')
| -rw-r--r-- | libhw/rp2040_hwspi.c | 8 | ||||
| -rw-r--r-- | libhw/rp2040_include/libhw/rp2040_hwspi.h | 12 |
2 files changed, 12 insertions, 8 deletions
diff --git a/libhw/rp2040_hwspi.c b/libhw/rp2040_hwspi.c index da7ee78..47dfc97 100644 --- a/libhw/rp2040_hwspi.c +++ b/libhw/rp2040_hwspi.c @@ -40,14 +40,6 @@ void _rp2040_hwspi_init(struct rp2040_hwspi *self, assert(pin_mosi != pin_cs); assert(pin_clk != pin_cs); - /* I know we called this "hwspi", but we're actually going to - * disconnect the CS pin from the PL022 SSP and manually drive - * it from software. This is because the PL022 has a maximum - * of 16-bit frames, while we need to be able to do *at least* - * 32-bit frames (and ideally, much larger). By managing it - * ourselves, we can just keep CS pulled low extra-long, - * making the frame extra-long. */ - /* Regarding the constraints on pin assignments: see the * RP2040 datasheet, table 2, in ยง1.4.3 "GPIO Functions". */ switch (inst_num) { diff --git a/libhw/rp2040_include/libhw/rp2040_hwspi.h b/libhw/rp2040_include/libhw/rp2040_hwspi.h index 19fb4ba..7c4991b 100644 --- a/libhw/rp2040_include/libhw/rp2040_hwspi.h +++ b/libhw/rp2040_include/libhw/rp2040_hwspi.h @@ -41,6 +41,18 @@ struct rp2040_hwspi { * * There is no bit-order argument; the RP2040's hardware SPI always * uses MSB-first bit order. + * + * I know we called this "hwspi", but we're actually going to + * disconnect the CS pin from the PL022 SSP and manually GPIO it from + * the CPU. This is because the PL022 has a maximum of 16-bit frames, + * but we need to be able to do *at least* 32-bit frames (and ideally, + * much larger). By managing it ourselves, we can just keep CS pulled + * low extra-long, making the frame extra-long. However, this means + * that we can't SPI so fast that the CPU can't do things in time; + * experimentally much faster than 60MHz seems to be when I start + * getting mangled messages. We wouldn't have this speed limit with a + * PIO-based SPI driver, because it could toggle CLK and CS in + * lock-step with receiving data from the FIFO. */ #define rp2040_hwspi_init(self, name, \ inst_num, mode, baudrate_hz, \ |