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@@ -87,3 +87,59 @@ these first two, but not the @50Hz one. https://forums.parallax.com/discussion/download/128730/Hdmi-1.4-1000008562-6364143185282736974850538.pdf https://ia803002.us.archive.org/1/items/CEA-861-D/CEA-861-D.pdf + +The RP2040 has several clocks: + +Sources: + +- GPCLK0 (GPIO-based clock 0) +- GPCLK1 (GPIO-based clock 1) +- XOSC (External (Crystal) Oscillator) + + System PLL + + USB PLL +- ROSC (Ring Oscillator) + +These can be muxed onto several clocks which each have dividers (and +most of them enable/disable too): + +- clk_gpout0 (GPIO Muxing) +- clk_gpout1 (GPIO Muxing) +- clk_gpout2 (GPIO Muxing) +- clk_gpout3 (GPIO Muxing) +- clk_adc (ADC) +- clk_usb (USB) +- clk_RTC (RTC) +- clk_peri (UART and SPI) +- clk_sys (CPU, bus, RAM) +- clk_ref (watchdog and timers) + +``` +SSP = ARM Primecell Synchronous Serial Port + ^ ^ ^ +``` + +- SPI (Serial Peripheral Interface - Motorola) +- SSI (Synchronous Serial Interface - Texas Instruments) +- Microwire (National Semiconductor) + +| `sclk` | `SSPCLKOUT` | `SSP_CLK_OUT` | SSP clock output | +| `ss_n` | `SSPFSSOUT` | `SSP_FSS_OUT` | SSP frame/slave select output | +| `tx` | `SSPTXD` | `SSP_TX_D` | SSP transmit data | +| `rd` | `SSPRXD` | `SSP_RX_D` | SSP receive data | + +"The SPI uses `clk_peri` as its reference clock for SPI timing, and is +referred to as `SSPCLK` in the following sections. `clk_sys` is used +as the bus clock, and is referred to as `PCLK` in the following +sections" wut does that mean + +8 16-bit values in both the TX buffer and the RX buffer + + +---- + +The theoretical max rate of the the W5500 is just shy of 80 Mb/s = 10 MB/s + +IDK about HDMI compression yet, but naively uncompressed we're looking +at wanting to shove ~60 MB/s (480 Mb/s). + +Compression is an optional feature introduced in HDMI 2.1 :( |