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-rw-r--r--libhw/rp2040_include/libhw/rp2040_hwspi.h78
-rw-r--r--libhw/rp2040_include/libhw/rp2040_hwtimer.h26
-rw-r--r--libhw/rp2040_include/libhw/w5500.h98
3 files changed, 0 insertions, 202 deletions
diff --git a/libhw/rp2040_include/libhw/rp2040_hwspi.h b/libhw/rp2040_include/libhw/rp2040_hwspi.h
deleted file mode 100644
index 7c4991b..0000000
--- a/libhw/rp2040_include/libhw/rp2040_hwspi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* libhw/rp2040_hwspi.h - <libhw/generic/spi.h> implementation for the RP2040's ARM Primecell SSP (PL022)
- *
- * Copyright (C) 2024 Luke T. Shumaker <lukeshu@lukeshu.com>
- * SPDX-License-Identifier: AGPL-3.0-or-later
- */
-
-#ifndef _LIBHW_RP2040_HWSPI_H_
-#define _LIBHW_RP2040_HWSPI_H_
-
-#include <pico/binary_info.h> /* for bi_* */
-
-#include <libmisc/private.h>
-
-#include <libhw/generic/spi.h>
-
-enum rp2040_hwspi_instance {
- RP2040_HWSPI_0 = 0,
- RP2040_HWSPI_1 = 1,
-};
-
-struct rp2040_hwspi {
- implements_spi;
-
- BEGIN_PRIVATE(LIBHW_RP2040_HWSPI_H)
- void /*spi_inst_t*/ *inst;
- uint pin_cs;
- END_PRIVATE(LIBHW_RP2040_HWSPI_H)
-};
-
-/**
- * Initialize an instance of `struct rp2040_hwspi`.
- *
- * @param self : struct rp2040_hwspi : the structure to initialize
- * @param name : char * : a name for the SPI port; to include in the bininfo
- * @param inst_num : enum rp2040_hwspi_instance : the PL220 instance number; RP2040_HWSPI_{0,1}
- * @param mode : enum spi_mode : the SPI mode; SPI_MODE_{0..3}
- * @param pin_miso : uint : pin number; 0, 4, 16, or 20 for _HWSPI_0; 8, 12, 24, or 28 for _HWSPI_1
- * @param pin_mosi : uint : pin number; 3, 7, 19, or 23 for _HWSPI_0; 11, 15, or 27 for _HWSPI_1
- * @param pin_clk : uint : pin number; 2, 6, 18, or 22 for _HWSPI_0; 10, 14, or 26 for _HWSPI_1
- * @param pin_cs : uint : pin number; any unused GPIO pin
- *
- * There is no bit-order argument; the RP2040's hardware SPI always
- * uses MSB-first bit order.
- *
- * I know we called this "hwspi", but we're actually going to
- * disconnect the CS pin from the PL022 SSP and manually GPIO it from
- * the CPU. This is because the PL022 has a maximum of 16-bit frames,
- * but we need to be able to do *at least* 32-bit frames (and ideally,
- * much larger). By managing it ourselves, we can just keep CS pulled
- * low extra-long, making the frame extra-long. However, this means
- * that we can't SPI so fast that the CPU can't do things in time;
- * experimentally much faster than 60MHz seems to be when I start
- * getting mangled messages. We wouldn't have this speed limit with a
- * PIO-based SPI driver, because it could toggle CLK and CS in
- * lock-step with receiving data from the FIFO.
- */
-#define rp2040_hwspi_init(self, name, \
- inst_num, mode, baudrate_hz, \
- pin_miso, pin_mosi, pin_clk, pin_cs) \
- do { \
- bi_decl(bi_4pins_with_names(pin_miso, name" SPI MISO", \
- pin_mosi, name" SPI MOSI", \
- pin_mosi, name" SPI CLK", \
- pin_mosi, name" SPI CS")); \
- _rp2040_hwspi_init(self, \
- inst_num, mode, baudrate_hz, \
- pin_miso, pin_mosi, pin_clk, pin_cs); \
- } while(0)
-void _rp2040_hwspi_init(struct rp2040_hwspi *self,
- enum rp2040_hwspi_instance inst_num,
- enum spi_mode mode,
- uint baudrate_hz,
- uint pin_miso,
- uint pin_mosi,
- uint pin_clk,
- uint pin_cs);
-
-#endif /* _LIBHW_RP2040_HWSPI_H_ */
diff --git a/libhw/rp2040_include/libhw/rp2040_hwtimer.h b/libhw/rp2040_include/libhw/rp2040_hwtimer.h
deleted file mode 100644
index 6710ab1..0000000
--- a/libhw/rp2040_include/libhw/rp2040_hwtimer.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* libhw/rp2040_hwtimer.h - <libhw/generic/alarmclock.h> implementation for the RP2040's hardware timer
- *
- * Copyright (C) 2024 Luke T. Shumaker <lukeshu@lukeshu.com>
- * SPDX-License-Identifier: AGPL-3.0-or-later
- */
-
-#ifndef _LIBHW_RP2040_HWTIMER_H_
-#define _LIBHW_RP2040_HWTIMER_H_
-
-#include <libhw/generic/alarmclock.h>
-
-/**
- * The RP2040 has one system "timer" (which we also use for
- * ./rp2040_bootclock.c) with 4 alarm interrupts.
- */
-enum rp2040_hwalarm_instance {
- RP2040_HWALARM_0 = 0,
- RP2040_HWALARM_1 = 1,
- RP2040_HWALARM_2 = 2,
- RP2040_HWALARM_3 = 3,
- _RP2040_HWALARM_NUM,
-};
-
-implements_alarmclock *rp2040_hwtimer(enum rp2040_hwalarm_instance alarm_num);
-
-#endif /* _LIBHW_RP2040_HWTIMER_H_ */
diff --git a/libhw/rp2040_include/libhw/w5500.h b/libhw/rp2040_include/libhw/w5500.h
deleted file mode 100644
index 80366a0..0000000
--- a/libhw/rp2040_include/libhw/w5500.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* libhw/w5500.h - <libhw/generic/net.h> implementation for the WIZnet W5500 chip
- *
- * Copyright (C) 2024 Luke T. Shumaker <lukeshu@lukeshu.com>
- * SPDX-License-Identifier: AGPL-3.0-or-later
- */
-
-#ifndef _LIBHW_W5500_H_
-#define _LIBHW_W5500_H_
-
-#include <pico/binary_info.h> /* for bi_* */
-
-#include <libcr_ipc/chan.h>
-#include <libcr_ipc/mutex.h>
-#include <libcr_ipc/sema.h>
-#include <libmisc/private.h>
-
-#include <libhw/generic/net.h>
-#include <libhw/generic/spi.h>
-
-CR_CHAN_DECLARE(_w5500_sockintr_ch, uint8_t)
-
-struct _w5500_socket {
- /* const-after-init */
- implements_net_stream_listener implements_net_stream_listener;
- implements_net_stream_conn implements_net_stream_conn;
- implements_net_packet_conn implements_net_packet_conn;
- BEGIN_PRIVATE(LIBHW_W5500_H)
- uint8_t socknum;
-
- /* mutable */
- struct _w5500_socket *next_free;
- enum {
- W5500_MODE_NONE = 0,
- W5500_MODE_TCP,
- W5500_MODE_UDP,
- } mode;
- uint16_t port; /* MODE_{TCP,UDP} */
- uint64_t read_deadline_ns; /* MODE_{TCP,UDP} */
- cr_sema_t listen_sema; /* MODE_TCP */
- cr_sema_t read_sema; /* MODE_{TCP,UDP} */
- _w5500_sockintr_ch_t write_ch; /* MODE_{TCP,UDP} */
- bool list_open, read_open, write_open; /* MODE_TCP */
-
- cr_mutex_t cmd_mu;
- END_PRIVATE(LIBHW_W5500_H)
-};
-
-struct w5500 {
- /* const-after-init */
- implements_net_iface;
- BEGIN_PRIVATE(LIBHW_W5500_H)
- implements_spi *spidev;
- uint pin_intr;
- uint pin_reset;
- struct net_eth_addr hwaddr;
-
- /* mutable */
- uint16_t next_local_port;
- struct _w5500_socket sockets[8];
- struct _w5500_socket *free;
- cr_sema_t intr;
- END_PRIVATE(LIBHW_W5500_H)
-};
-
-/**
- * Initialize a WIZnet W5500 Ethernet-and-TCP/IP-offload chip.
- *
- * The W5500 has 3 lines of communication with the MCU:
- *
- * - An SPI-based RPC protocol:
- * + mode: mode 0 or mode 3
- * + bit-order: MSB-first
- * + clock frequency: 33.3MHz - 80MHz
- * - An interrupt pin that it pulls low when an event happens (to let
- * the MCU know that it should do an SPI RPC "get" to see what
- * happened.)
- * - A reset pin that the MCU can pull low to reset the W5500.
- */
-#define w5500_init(self, name, spi, pin_intr, pin_reset, eth_addr) do { \
- bi_decl(bi_2pins_with_names(pin_intr, name" interrupt", \
- pin_reset, name" reset")); \
- _w5500_init(self, spi, pin_intr, pin_reset, eth_addr); \
- } while (0)
-void _w5500_init(struct w5500 *self,
- implements_spi *spi, uint pin_intr, uint pin_reset,
- struct net_eth_addr addr);
-
-/**
- * TODO.
- */
-void w5500_hard_reset(struct w5500 *self);
-
-/**
- * TODO.
- */
-void w5500_soft_reset(struct w5500 *self);
-
-#endif /* _LIBHW_W5500_H_ */
generated by cgit v1.2.3-2-g168b (git 2.25.1) at 2025-04-13 13:07:59 +0000