libhw: Update comments and asserts about clock rate

1 files changed, 3 insertions, 3 deletions

diff --git a/libhw/w5500.c b/libhw/w5500.c
index 0f15785..c4d36f3 100644
--- a/libhw/w5500.c
+++ b/libhw/w5500.c
@@ -348,9 +348,9 @@ static void w5500_post_reset(struct w5500 *chip) {
 	w5500ll_write_common_reg(chip->spidev, eth_addr, chip->hwaddr);
 
 	/* The RP2040 needs a 1/sys_clk hysteresis between interrupts
-	 * for us to notice them.  At the maximum-rated clock-rate of
-	 * 133MHz, that means 7.5ns (but the sbc-harness overclocks
-	 * the RP2040, so we could get away with even shorter).
+	 * for us to notice them.  At the default clock-rate of
+	 * 125MHz, that means 8ns; and at the maximum-rated clock-rate
+	 * of 200MHz, that means 5ns.
 	 *
 	 * If intlevel is non-zero, then the hysteresis is
 	 * (intlevel+1)*4/(150MHz), or (intlevel+1)*26.7ns; so even