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authorLuke T. Shumaker <lukeshu@lukeshu.com>2025-03-04 00:18:23 -0700
committerLuke T. Shumaker <lukeshu@lukeshu.com>2025-03-04 00:18:23 -0700
commit47cee5df1e5e63a8d0a5f1b634ac6d4e1ff00af7 (patch)
treed72daabeedecbc397cdce739639f8cf2cb947685 /libhw/w5500.c
parent355d7a495b0ca1a622d600427a8c737f3207a803 (diff)
parent3f49a57b99e7fe5aafa73e70ed146d98b1ae174c (diff)
Merge branch 'lukeshu/dma'
Diffstat (limited to 'libhw/w5500.c')
-rw-r--r--libhw/w5500.c25
1 files changed, 22 insertions, 3 deletions
diff --git a/libhw/w5500.c b/libhw/w5500.c
index b4ad86b..c4d36f3 100644
--- a/libhw/w5500.c
+++ b/libhw/w5500.c
@@ -96,6 +96,9 @@
#ifndef CONFIG_W5500_LOCAL_PORT_MAX
#error config.h must define CONFIG_W5500_LOCAL_PORT_MAX
#endif
+#ifndef CONFIG_W5500_VALIDATE_SPI
+ #error config.h must define CONFIG_W5500_VALIDATE_SPI
+#endif
#ifndef CONFIG_W5500_DEBUG
#error config.h must define CONFIG_W5500_DEBUG
#endif
@@ -312,6 +315,22 @@ void _w5500_init(struct w5500 *chip,
};
}
+#if CONFIG_W5500_VALIDATE_SPI
+ /* Validate that SPI works correctly. */
+ bool spi_ok = true;
+ for (uint16_t a = 0; a < 0x100; a++) {
+ w5500ll_write_sock_reg(chip->spidev, 0, mode, a);
+ uint8_t b = w5500ll_read_sock_reg(chip->spidev, 0, mode);
+ if (b != a) {
+ errorf("SPI to W5500 does not appear to be functional: wrote:0x%02"PRIx16" != read:0x%02"PRIx8, a, b);
+ spi_ok = false;
+ }
+ }
+ if (!spi_ok)
+ __lm_abort();
+ w5500ll_write_sock_reg(chip->spidev, 0, mode, 0);
+#endif
+
/* Initialize the hardware. */
gpioirq_set_and_enable_exclusive_handler(pin_intr, GPIO_IRQ_EDGE_FALL, w5500_intrhandler, chip);
gpio_set_dir(chip->pin_reset, GPIO_OUT);
@@ -329,9 +348,9 @@ static void w5500_post_reset(struct w5500 *chip) {
w5500ll_write_common_reg(chip->spidev, eth_addr, chip->hwaddr);
/* The RP2040 needs a 1/sys_clk hysteresis between interrupts
- * for us to notice them. At the maximum-rated clock-rate of
- * 133MHz, that means 7.5ns (but the sbc-harness overclocks
- * the RP2040, so we could get away with even shorter).
+ * for us to notice them. At the default clock-rate of
+ * 125MHz, that means 8ns; and at the maximum-rated clock-rate
+ * of 200MHz, that means 5ns.
*
* If intlevel is non-zero, then the hysteresis is
* (intlevel+1)*4/(150MHz), or (intlevel+1)*26.7ns; so even