diff options
| author | Luke T. Shumaker <lukeshu@lukeshu.com> | 2024-11-19 21:57:17 -0700 |
|---|---|---|
| committer | Luke T. Shumaker <lukeshu@lukeshu.com> | 2024-11-23 12:39:09 -0700 |
| commit | 910c85365ff3d7b2601132fd53542b6e594fa855 (patch) | |
| tree | dc21cf764e9e25d876a8a02b02fb28364c2be2bd /libhw/rp2040_include | |
| parent | 24cd8ca4ee1ea08526eb82e6c122870c86da5603 (diff) | |
Speed SPI back up
Diffstat (limited to 'libhw/rp2040_include')
| -rw-r--r-- | libhw/rp2040_include/libhw/rp2040_hwspi.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/libhw/rp2040_include/libhw/rp2040_hwspi.h b/libhw/rp2040_include/libhw/rp2040_hwspi.h index 19fb4ba..7c4991b 100644 --- a/libhw/rp2040_include/libhw/rp2040_hwspi.h +++ b/libhw/rp2040_include/libhw/rp2040_hwspi.h @@ -41,6 +41,18 @@ struct rp2040_hwspi { * * There is no bit-order argument; the RP2040's hardware SPI always * uses MSB-first bit order. + * + * I know we called this "hwspi", but we're actually going to + * disconnect the CS pin from the PL022 SSP and manually GPIO it from + * the CPU. This is because the PL022 has a maximum of 16-bit frames, + * but we need to be able to do *at least* 32-bit frames (and ideally, + * much larger). By managing it ourselves, we can just keep CS pulled + * low extra-long, making the frame extra-long. However, this means + * that we can't SPI so fast that the CPU can't do things in time; + * experimentally much faster than 60MHz seems to be when I start + * getting mangled messages. We wouldn't have this speed limit with a + * PIO-based SPI driver, because it could toggle CLK and CS in + * lock-step with receiving data from the FIFO. */ #define rp2040_hwspi_init(self, name, \ inst_num, mode, baudrate_hz, \ |