diff options
| author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-04-13 12:39:03 -0300 |
|---|---|---|
| committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-04-13 21:27:15 -0300 |
| commit | f62f8ff0be814cf39eff307bc8231cece266834c (patch) | |
| tree | fb18c95e7a083fb451fdd8be4f82e17bbee38f31 /kernels/linux-libre-lts-knock | |
| parent | ecbe4f91c7cd19fd04a2d72fdbb419a3eca4e7a2 (diff) | |
linux-libre-lts{,-knock}: add more patches and adapt sun5i-r8.dtsi for 4.1 kernels
Diffstat (limited to 'kernels/linux-libre-lts-knock')
11 files changed, 1378 insertions, 91 deletions
diff --git a/kernels/linux-libre-lts-knock/0001-ARM-sunxi-Add-R8-support.patch b/kernels/linux-libre-lts-knock/0001-ARM-sunxi-Add-R8-support.patch index 9f685790e..4d8194026 100644 --- a/kernels/linux-libre-lts-knock/0001-ARM-sunxi-Add-R8-support.patch +++ b/kernels/linux-libre-lts-knock/0001-ARM-sunxi-Add-R8-support.patch @@ -1,7 +1,7 @@ From bef6229f36c1c2ddae186f4e328c2359c1dad18d Mon Sep 17 00:00:00 2001 From: Maxime Ripard <maxime.ripard@free-electrons.com> Date: Tue, 9 Jun 2015 19:38:04 +0200 -Subject: [PATCH 1/3] ARM: sunxi: Add R8 support +Subject: [PATCH 1/9] ARM: sunxi: Add R8 support The R8 is a new Allwinner SoC based on the A13. While both are very similar, there's still a few differences. Introduce a new compatible to diff --git a/kernels/linux-libre-lts-knock/0002-ARM-sun5i-Add-CHIP-DTS.patch b/kernels/linux-libre-lts-knock/0002-ARM-sun5i-Add-CHIP-DTS.patch index 2ca192730..296182aa7 100644 --- a/kernels/linux-libre-lts-knock/0002-ARM-sun5i-Add-CHIP-DTS.patch +++ b/kernels/linux-libre-lts-knock/0002-ARM-sun5i-Add-CHIP-DTS.patch @@ -1,7 +1,7 @@ From 465a225fb2afb3ebf1becbe76d46b084d46f30a5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard <maxime.ripard@free-electrons.com> Date: Tue, 9 Jun 2015 19:38:43 +0200 -Subject: [PATCH 2/3] ARM: sun5i: Add C.H.I.P DTS +Subject: [PATCH 2/9] ARM: sun5i: Add C.H.I.P DTS The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack diff --git a/kernels/linux-libre-lts-knock/0003-ARM-sun5i-Add-R8-DTSI.patch b/kernels/linux-libre-lts-knock/0003-ARM-sun5i-Add-R8-DTSI.patch deleted file mode 100644 index bfa01eaa8..000000000 --- a/kernels/linux-libre-lts-knock/0003-ARM-sun5i-Add-R8-DTSI.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 49e4f3c3271e7eff2800596ba168c932d7d702b8 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard <maxime.ripard@free-electrons.com> -Date: Fri, 18 Sep 2015 09:09:34 +0200 -Subject: [PATCH 3/3] ARM: sun5i: Add R8 DTSI - -The R8 is very close to the A13, but it still has a few differences, -notably a composite output, which the A13 lacks. - -Add a DTSI based on the A13's to hold those differences. - -Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> -Reviewed-by: Chen-Yu Tsai <wens@csie.org> -Reviewed-by: Hans de Goede <hdegoede@redhat.com> ---- - arch/arm/boot/dts/sun5i-r8.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) - create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi - -diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi -new file mode 100644 -index 0000000..0ef8656 ---- /dev/null -+++ b/arch/arm/boot/dts/sun5i-r8.dtsi -@@ -0,0 +1,59 @@ -+/* -+ * Copyright 2015 Free Electrons -+ * Copyright 2015 NextThing Co -+ * -+ * Maxime Ripard <maxime.ripard@free-electrons.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "sun5i-a13.dtsi" -+ -+/ { -+ chosen { -+ framebuffer@1 { -+ compatible = "allwinner,simple-framebuffer", -+ "simple-framebuffer"; -+ allwinner,pipeline = "de_be0-lcd0-tve0"; -+ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, -+ <&ahb_gates 44>; -+ status = "disabled"; -+ }; -+ }; -+}; --- -cgit v0.12 - diff --git a/kernels/linux-libre-lts-knock/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch b/kernels/linux-libre-lts-knock/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch new file mode 100644 index 000000000..e9b2c566c --- /dev/null +++ b/kernels/linux-libre-lts-knock/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch @@ -0,0 +1,32 @@ +From e54693ed82ae0fee934a21328536751afd293c80 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Tue, 28 Jul 2015 10:37:01 +0200 +Subject: [PATCH 3/9] ARM: sun5i: chip: Enable the audio codec + +The CHIP v0.2 has a composite output on a mini-jack connector, the audio +part being provided by the on-SoC codec. Enable it. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Acked-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts +index abf3ccb..530ab28 100644 +--- a/arch/arm/boot/dts/sun5i-r8-chip.dts ++++ b/arch/arm/boot/dts/sun5i-r8-chip.dts +@@ -66,6 +66,10 @@ + }; + }; + ++&codec { ++ status = "okay"; ++}; ++ + &ehci0 { + status = "okay"; + }; +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0004-ARM-sun5i-Add-R8-DTSI.patch b/kernels/linux-libre-lts-knock/0004-ARM-sun5i-Add-R8-DTSI.patch new file mode 100644 index 000000000..5c97fd48c --- /dev/null +++ b/kernels/linux-libre-lts-knock/0004-ARM-sun5i-Add-R8-DTSI.patch @@ -0,0 +1,779 @@ +From 49e4f3c3271e7eff2800596ba168c932d7d702b8 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Fri, 18 Sep 2015 09:09:34 +0200 +Subject: [PATCH 4/9] ARM: sun5i: Add R8 DTSI + +The R8 is very close to the A13, but it still has a few differences, +notably a composite output, which the A13 lacks. + +Add a DTSI based on the A13's to hold those differences. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Reviewed-by: Chen-Yu Tsai <wens@csie.org> +Reviewed-by: Hans de Goede <hdegoede@redhat.com> +Reviewed-by: André Silva <emulatorman@parabola.nu> +Reviewed-by: Márcio Silva <coadde@parabola.nu> +--- + arch/arm/boot/dts/sun5i-r8.dtsi | 750 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 750 insertions(+) + create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi + +diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi +new file mode 100644 +index 0000000..75a9960 +--- /dev/null ++++ b/arch/arm/boot/dts/sun5i-r8.dtsi +@@ -0,0 +1,750 @@ ++/* ++ * Copyright 2015 Free Electrons ++ * Copyright 2015 NextThing Co ++ * ++ * Maxime Ripard <maxime.ripard@free-electrons.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "skeleton.dtsi" ++ ++#include <dt-bindings/thermal/thermal.h> ++ ++#include <dt-bindings/clock/sun4i-a10-pll2.h> ++#include <dt-bindings/dma/sun4i-a10.h> ++#include <dt-bindings/pinctrl/sun4i-a10.h> ++ ++/ { ++ interrupt-parent = <&intc>; ++ ++ chosen { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ framebuffer@0 { ++ compatible = "allwinner,simple-framebuffer", ++ "simple-framebuffer"; ++ allwinner,pipeline = "de_be0-lcd0"; ++ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; ++ status = "disabled"; ++ }; ++ ++ framebuffer@1 { ++ compatible = "allwinner,simple-framebuffer", ++ "simple-framebuffer"; ++ allwinner,pipeline = "de_be0-lcd0-tve0"; ++ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, ++ <&ahb_gates 44>; ++ status = "disabled"; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a8"; ++ reg = <0x0>; ++ clocks = <&cpu>; ++ clock-latency = <244144>; /* 8 32k periods */ ++ operating-points = < ++ /* kHz uV */ ++ 1008000 1400000 ++ 912000 1350000 ++ 864000 1300000 ++ 624000 1200000 ++ 576000 1200000 ++ 432000 1200000 ++ >; ++ #cooling-cells = <2>; ++ cooling-min-level = <0>; ++ cooling-max-level = <5>; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal { ++ /* milliseconds */ ++ polling-delay-passive = <250>; ++ polling-delay = <1000>; ++ thermal-sensors = <&rtp>; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ /* milliCelsius */ ++ temperature = <850000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ /* milliCelsius */ ++ temperature = <100000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ clocks { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ /* ++ * This is a dummy clock, to be used as placeholder on ++ * other mux clocks when a specific parent clock is not ++ * yet implemented. It should be dropped when the driver ++ * is complete. ++ */ ++ dummy: dummy { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ osc24M: clk@01c20050 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-osc-clk"; ++ reg = <0x01c20050 0x4>; ++ clock-frequency = <24000000>; ++ clock-output-names = "osc24M"; ++ }; ++ ++ osc32k: clk@0 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "osc32k"; ++ }; ++ ++ pll1: clk@01c20000 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-pll1-clk"; ++ reg = <0x01c20000 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll1"; ++ }; ++ ++ pll2: clk@01c20008 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun5i-a13-pll2-clk"; ++ reg = <0x01c20008 0x8>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll2-1x", "pll2-2x", ++ "pll2-4x", "pll2-8x"; ++ }; ++ ++ pll4: clk@01c20018 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-pll1-clk"; ++ reg = <0x01c20018 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll4"; ++ }; ++ ++ pll5: clk@01c20020 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-pll5-clk"; ++ reg = <0x01c20020 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll5_ddr", "pll5_other"; ++ }; ++ ++ pll6: clk@01c20028 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-pll6-clk"; ++ reg = <0x01c20028 0x4>; ++ clocks = <&osc24M>; ++ clock-output-names = "pll6_sata", "pll6_other", "pll6"; ++ }; ++ ++ /* dummy is 200M */ ++ cpu: cpu@01c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-cpu-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; ++ clock-output-names = "cpu"; ++ }; ++ ++ axi: axi@01c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-axi-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&cpu>; ++ clock-output-names = "axi"; ++ }; ++ ++ axi_gates: clk@01c2005c { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-axi-gates-clk"; ++ reg = <0x01c2005c 0x4>; ++ clocks = <&axi>; ++ clock-output-names = "axi_dram"; ++ }; ++ ++ ahb: ahb@01c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-ahb-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&axi>; ++ clock-output-names = "ahb"; ++ }; ++ ++ ahb_gates: clk@01c20060 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun5i-a13-ahb-gates-clk"; ++ reg = <0x01c20060 0x8>; ++ clocks = <&ahb>; ++ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", ++ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", ++ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", ++ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", ++ "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", ++ "ahb_de_fe", "ahb_iep", "ahb_mali400"; ++ }; ++ ++ apb0: apb0@01c20054 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-apb0-clk"; ++ reg = <0x01c20054 0x4>; ++ clocks = <&ahb>; ++ clock-output-names = "apb0"; ++ }; ++ ++ apb0_gates: clk@01c20068 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun5i-a13-apb0-gates-clk"; ++ reg = <0x01c20068 0x4>; ++ clocks = <&apb0>; ++ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; ++ }; ++ ++ apb1: clk@01c20058 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-apb1-clk"; ++ reg = <0x01c20058 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&osc32k>; ++ clock-output-names = "apb1"; ++ }; ++ ++ apb1_gates: clk@01c2006c { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun5i-a13-apb1-gates-clk"; ++ reg = <0x01c2006c 0x4>; ++ clocks = <&apb1>; ++ clock-output-names = "apb1_i2c0", "apb1_i2c1", ++ "apb1_i2c2", "apb1_uart1", "apb1_uart3"; ++ }; ++ ++ nand_clk: clk@01c20080 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c20080 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "nand"; ++ }; ++ ++ ms_clk: clk@01c20084 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c20084 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "ms"; ++ }; ++ ++ mmc0_clk: clk@01c20088 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-mmc-clk"; ++ reg = <0x01c20088 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "mmc0", ++ "mmc0_output", ++ "mmc0_sample"; ++ }; ++ ++ mmc1_clk: clk@01c2008c { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-mmc-clk"; ++ reg = <0x01c2008c 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "mmc1", ++ "mmc1_output", ++ "mmc1_sample"; ++ }; ++ ++ mmc2_clk: clk@01c20090 { ++ #clock-cells = <1>; ++ compatible = "allwinner,sun4i-a10-mmc-clk"; ++ reg = <0x01c20090 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "mmc2", ++ "mmc2_output", ++ "mmc2_sample"; ++ }; ++ ++ ts_clk: clk@01c20098 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c20098 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "ts"; ++ }; ++ ++ ss_clk: clk@01c2009c { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c2009c 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "ss"; ++ }; ++ ++ spi0_clk: clk@01c200a0 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200a0 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "spi0"; ++ }; ++ ++ spi1_clk: clk@01c200a4 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200a4 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "spi1"; ++ }; ++ ++ spi2_clk: clk@01c200a8 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200a8 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "spi2"; ++ }; ++ ++ ir0_clk: clk@01c200b0 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01c200b0 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "ir0"; ++ }; ++ ++ usb_clk: clk@01c200cc { ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ compatible = "allwinner,sun5i-a13-usb-clk"; ++ reg = <0x01c200cc 0x4>; ++ clocks = <&pll6 1>; ++ clock-output-names = "usb_ohci0", "usb_phy"; ++ }; ++ ++ codec_clk: clk@01c20140 { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun4i-a10-codec-clk"; ++ reg = <0x01c20140 0x4>; ++ clocks = <&pll2 SUN4I_A10_PLL2_1X>; ++ clock-output-names = "codec"; ++ }; ++ ++ mbus_clk: clk@01c2015c { ++ #clock-cells = <0>; ++ compatible = "allwinner,sun5i-a13-mbus-clk"; ++ reg = <0x01c2015c 0x4>; ++ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; ++ clock-output-names = "mbus"; ++ }; ++ }; ++ ++ soc@01c00000 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ sram-controller@01c00000 { ++ compatible = "allwinner,sun4i-a10-sram-controller"; ++ reg = <0x01c00000 0x30>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ sram_a: sram@00000000 { ++ compatible = "mmio-sram"; ++ reg = <0x00000000 0xc000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x00000000 0xc000>; ++ }; ++ ++ sram_d: sram@00010000 { ++ compatible = "mmio-sram"; ++ reg = <0x00010000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x00010000 0x1000>; ++ ++ otg_sram: sram-section@0000 { ++ compatible = "allwinner,sun4i-a10-sram-d"; ++ reg = <0x0000 0x1000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ dma: dma-controller@01c02000 { ++ compatible = "allwinner,sun4i-a10-dma"; ++ reg = <0x01c02000 0x1000>; ++ interrupts = <27>; ++ clocks = <&ahb_gates 6>; ++ #dma-cells = <2>; ++ }; ++ ++ spi0: spi@01c05000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c05000 0x1000>; ++ interrupts = <10>; ++ clocks = <&ahb_gates 20>, <&spi0_clk>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma SUN4I_DMA_DEDICATED 27>, ++ <&dma SUN4I_DMA_DEDICATED 26>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@01c06000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c06000 0x1000>; ++ interrupts = <11>; ++ clocks = <&ahb_gates 21>, <&spi1_clk>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma SUN4I_DMA_DEDICATED 9>, ++ <&dma SUN4I_DMA_DEDICATED 8>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc0: mmc@01c0f000 { ++ compatible = "allwinner,sun5i-a13-mmc"; ++ reg = <0x01c0f000 0x1000>; ++ clocks = <&ahb_gates 8>, ++ <&mmc0_clk 0>, ++ <&mmc0_clk 1>, ++ <&mmc0_clk 2>; ++ clock-names = "ahb", ++ "mmc", ++ "output", ++ "sample"; ++ interrupts = <32>; ++ status = "disabled"; ++ }; ++ ++ mmc2: mmc@01c11000 { ++ compatible = "allwinner,sun5i-a13-mmc"; ++ reg = <0x01c11000 0x1000>; ++ clocks = <&ahb_gates 10>, ++ <&mmc2_clk 0>, ++ <&mmc2_clk 1>, ++ <&mmc2_clk 2>; ++ clock-names = "ahb", ++ "mmc", ++ "output", ++ "sample"; ++ interrupts = <34>; ++ status = "disabled"; ++ }; ++ ++ usb_otg: usb@01c13000 { ++ compatible = "allwinner,sun4i-a10-musb"; ++ reg = <0x01c13000 0x0400>; ++ clocks = <&ahb_gates 0>; ++ interrupts = <38>; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ allwinner,sram = <&otg_sram 1>; ++ status = "disabled"; ++ }; ++ ++ usbphy: phy@01c13400 { ++ #phy-cells = <1>; ++ compatible = "allwinner,sun5i-a13-usb-phy"; ++ reg = <0x01c13400 0x10 0x01c14800 0x4>; ++ reg-names = "phy_ctrl", "pmu1"; ++ clocks = <&usb_clk 8>; ++ clock-names = "usb_phy"; ++ resets = <&usb_clk 0>, <&usb_clk 1>; ++ reset-names = "usb0_reset", "usb1_reset"; ++ status = "disabled"; ++ }; ++ ++ ehci0: usb@01c14000 { ++ compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; ++ reg = <0x01c14000 0x100>; ++ interrupts = <39>; ++ clocks = <&ahb_gates 1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@01c14400 { ++ compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; ++ reg = <0x01c14400 0x100>; ++ interrupts = <40>; ++ clocks = <&usb_clk 6>, <&ahb_gates 2>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@01c17000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c17000 0x1000>; ++ interrupts = <12>; ++ clocks = <&ahb_gates 22>, <&spi2_clk>; ++ clock-names = "ahb", "mod"; ++ dmas = <&dma SUN4I_DMA_DEDICATED 29>, ++ <&dma SUN4I_DMA_DEDICATED 28>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ intc: interrupt-controller@01c20400 { ++ compatible = "allwinner,sun4i-a10-ic"; ++ reg = <0x01c20400 0x400>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ pio: pinctrl@01c20800 { ++ compatible = "allwinner,sun5i-a13-pinctrl"; ++ reg = <0x01c20800 0x400>; ++ interrupts = <28>; ++ clocks = <&apb0_gates 5>; ++ gpio-controller; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ #size-cells = <0>; ++ #gpio-cells = <3>; ++ ++ uart1_pins_a: uart1@0 { ++ allwinner,pins = "PE10", "PE11"; ++ allwinner,function = "uart1"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ uart1_pins_b: uart1@1 { ++ allwinner,pins = "PG3", "PG4"; ++ allwinner,function = "uart1"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ uart3_pins_a: uart3@0 { ++ allwinner,pins = "PG9", "PG10"; ++ allwinner,function = "uart3"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ uart3_pins_cts_rts_a: uart3-cts-rts@0 { ++ allwinner,pins = "PG11", "PG12"; ++ allwinner,function = "uart3"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ i2c0_pins_a: i2c0@0 { ++ allwinner,pins = "PB0", "PB1"; ++ allwinner,function = "i2c0"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ i2c1_pins_a: i2c1@0 { ++ allwinner,pins = "PB15", "PB16"; ++ allwinner,function = "i2c1"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ i2c2_pins_a: i2c2@0 { ++ allwinner,pins = "PB17", "PB18"; ++ allwinner,function = "i2c2"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ mmc0_pins_a: mmc0@0 { ++ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; ++ allwinner,function = "mmc0"; ++ allwinner,drive = <SUN4I_PINCTRL_30_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ }; ++ ++ timer@01c20c00 { ++ compatible = "allwinner,sun4i-a10-timer"; ++ reg = <0x01c20c00 0x90>; ++ interrupts = <22>; ++ clocks = <&osc24M>; ++ }; ++ ++ wdt: watchdog@01c20c90 { ++ compatible = "allwinner,sun4i-a10-wdt"; ++ reg = <0x01c20c90 0x10>; ++ }; ++ ++ lradc: lradc@01c22800 { ++ compatible = "allwinner,sun4i-a10-lradc-keys"; ++ reg = <0x01c22800 0x100>; ++ interrupts = <31>; ++ status = "disabled"; ++ }; ++ ++ codec: codec@01c22c00 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun4i-a10-codec"; ++ reg = <0x01c22c00 0x40>; ++ interrupts = <30>; ++ clocks = <&apb0_gates 0>, <&codec_clk>; ++ clock-names = "apb", "codec"; ++ dmas = <&dma SUN4I_DMA_NORMAL 19>, ++ <&dma SUN4I_DMA_NORMAL 19>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ sid: eeprom@01c23800 { ++ compatible = "allwinner,sun4i-a10-sid"; ++ reg = <0x01c23800 0x10>; ++ }; ++ ++ rtp: rtp@01c25000 { ++ compatible = "allwinner,sun4i-a10-ts"; ++ reg = <0x01c25000 0x100>; ++ interrupts = <29>; ++ #thermal-sensor-cells = <0>; ++ }; ++ ++ uart1: serial@01c28400 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28400 0x400>; ++ interrupts = <2>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&apb1_gates 17>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@01c28c00 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x01c28c00 0x400>; ++ interrupts = <4>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clocks = <&apb1_gates 19>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@01c2ac00 { ++ compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; ++ reg = <0x01c2ac00 0x400>; ++ interrupts = <7>; ++ clocks = <&apb1_gates 0>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c1: i2c@01c2b000 { ++ compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; ++ reg = <0x01c2b000 0x400>; ++ interrupts = <8>; ++ clocks = <&apb1_gates 1>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c2: i2c@01c2b400 { ++ compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c"; ++ reg = <0x01c2b400 0x400>; ++ interrupts = <9>; ++ clocks = <&apb1_gates 2>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ timer@01c60000 { ++ compatible = "allwinner,sun5i-a13-hstimer"; ++ reg = <0x01c60000 0x1000>; ++ interrupts = <82>, <83>; ++ clocks = <&ahb_gates 28>; ++ }; ++ }; ++}; +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch b/kernels/linux-libre-lts-knock/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch new file mode 100644 index 000000000..e1c185e0e --- /dev/null +++ b/kernels/linux-libre-lts-knock/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch @@ -0,0 +1,299 @@ +From 460d0d444822e9032a2573fc051b45c68b89a97a Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Fri, 18 Jul 2014 15:48:35 -0300 +Subject: [PATCH 5/9] clk: sunxi: Add a driver for the PLL2 + +The PLL2 on the A10 and later SoCs is the clock used for all the audio +related operations. + +This clock has a somewhat complex output tree, with three outputs (2X, 4X +and 8X) with a fixed divider from the base clock, and an output (1X) with a +post divider. + +However, we can simplify things since the 1X divider can be fixed, and we +end up by having a base clock not exposed to any device (or at least +directly, since the 4X output doesn't have any divider), and 4 fixed +divider clocks that will be exposed. + +This clock seems to have been introduced, at least in this form, in the +revision B of the A10, but we don't have any information on the clock used +on the revision A. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Reviewed-by: Chen-Yu Tsai <wens@csie.org> +--- + drivers/clk/sunxi/Makefile | 1 + + drivers/clk/sunxi/clk-a10-pll2.c | 188 +++++++++++++++++++++++++++++ + include/dt-bindings/clock/sun4i-a10-pll2.h | 53 ++++++++ + 3 files changed, 242 insertions(+) + create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c + create mode 100644 include/dt-bindings/clock/sun4i-a10-pll2.h + +diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile +index f5a35b8..c658a18 100644 +--- a/drivers/clk/sunxi/Makefile ++++ b/drivers/clk/sunxi/Makefile +@@ -4,6 +4,7 @@ + + obj-y += clk-sunxi.o clk-factors.o + obj-y += clk-a10-hosc.o ++obj-y += clk-a10-pll2.o + obj-y += clk-a20-gmac.o + obj-y += clk-mod0.o + obj-y += clk-simple-gates.o +diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c +new file mode 100644 +index 0000000..a57742a +--- /dev/null ++++ b/drivers/clk/sunxi/clk-a10-pll2.c +@@ -0,0 +1,188 @@ ++/* ++ * Copyright 2013 Emilio López ++ * Emilio López <emilio@elopez.com.ar> ++ * ++ * Copyright 2015 Maxime Ripard ++ * Maxime Ripard <maxime.ripard@free-electrons.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/clk-provider.h> ++#include <linux/of.h> ++#include <linux/of_address.h> ++#include <linux/slab.h> ++ ++#include <dt-bindings/clock/sun4i-a10-pll2.h> ++ ++#define SUN4I_PLL2_ENABLE 31 ++ ++#define SUN4I_PLL2_PRE_DIV_SHIFT 0 ++#define SUN4I_PLL2_PRE_DIV_WIDTH 5 ++#define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0) ++ ++#define SUN4I_PLL2_N_SHIFT 8 ++#define SUN4I_PLL2_N_WIDTH 7 ++#define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0) ++ ++#define SUN4I_PLL2_POST_DIV_SHIFT 26 ++#define SUN4I_PLL2_POST_DIV_WIDTH 4 ++#define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0) ++ ++#define SUN4I_PLL2_POST_DIV_VALUE 4 ++ ++#define SUN4I_PLL2_OUTPUTS 4 ++ ++static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); ++ ++static void __init sun4i_pll2_setup(struct device_node *node) ++{ ++ const char *clk_name = node->name, *parent; ++ struct clk **clks, *base_clk, *prediv_clk; ++ struct clk_onecell_data *clk_data; ++ struct clk_multiplier *mult; ++ struct clk_gate *gate; ++ void __iomem *reg; ++ u32 val; ++ ++ reg = of_io_request_and_map(node, 0, of_node_full_name(node)); ++ if (IS_ERR(reg)) ++ return; ++ ++ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); ++ if (!clk_data) ++ goto err_unmap; ++ ++ clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); ++ if (!clks) ++ goto err_free_data; ++ ++ parent = of_clk_get_parent_name(node, 0); ++ prediv_clk = clk_register_divider(NULL, "pll2-prediv", ++ parent, 0, reg, ++ SUN4I_PLL2_PRE_DIV_SHIFT, ++ SUN4I_PLL2_PRE_DIV_WIDTH, ++ CLK_DIVIDER_ONE_BASED | ++ CLK_DIVIDER_ALLOW_ZERO, ++ &sun4i_a10_pll2_lock); ++ if (!prediv_clk) { ++ pr_err("Couldn't register the prediv clock\n"); ++ goto err_free_array; ++ } ++ ++ /* Setup the gate part of the PLL2 */ ++ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); ++ if (!gate) ++ goto err_unregister_prediv; ++ ++ gate->reg = reg; ++ gate->bit_idx = SUN4I_PLL2_ENABLE; ++ gate->lock = &sun4i_a10_pll2_lock; ++ ++ /* Setup the multiplier part of the PLL2 */ ++ mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); ++ if (!mult) ++ goto err_free_gate; ++ ++ mult->reg = reg; ++ mult->shift = SUN4I_PLL2_N_SHIFT; ++ mult->width = 7; ++ mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | ++ CLK_MULTIPLIER_ROUND_CLOSEST; ++ mult->lock = &sun4i_a10_pll2_lock; ++ ++ parent = __clk_get_name(prediv_clk); ++ base_clk = clk_register_composite(NULL, "pll2-base", ++ &parent, 1, ++ NULL, NULL, ++ &mult->hw, &clk_multiplier_ops, ++ &gate->hw, &clk_gate_ops, ++ CLK_SET_RATE_PARENT); ++ if (!base_clk) { ++ pr_err("Couldn't register the base multiplier clock\n"); ++ goto err_free_multiplier; ++ } ++ ++ parent = __clk_get_name(base_clk); ++ ++ /* ++ * PLL2-1x ++ * ++ * This is supposed to have a post divider, but we won't need ++ * to use it, we just need to initialise it to 4, and use a ++ * fixed divider. ++ */ ++ val = readl(reg); ++ val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); ++ val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT; ++ writel(val, reg); ++ ++ of_property_read_string_index(node, "clock-output-names", ++ SUN4I_A10_PLL2_1X, &clk_name); ++ clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, ++ parent, ++ CLK_SET_RATE_PARENT, ++ 1, ++ SUN4I_PLL2_POST_DIV_VALUE); ++ WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); ++ ++ /* ++ * PLL2-2x ++ * ++ * This clock doesn't use the post divider, and really is just ++ * a fixed divider from the PLL2 base clock. ++ */ ++ of_property_read_string_index(node, "clock-output-names", ++ SUN4I_A10_PLL2_2X, &clk_name); ++ clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, ++ parent, ++ CLK_SET_RATE_PARENT, ++ 1, 2); ++ WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); ++ ++ /* PLL2-4x */ ++ of_property_read_string_index(node, "clock-output-names", ++ SUN4I_A10_PLL2_4X, &clk_name); ++ clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, ++ parent, ++ CLK_SET_RATE_PARENT, ++ 1, 1); ++ WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); ++ ++ /* PLL2-8x */ ++ of_property_read_string_index(node, "clock-output-names", ++ SUN4I_A10_PLL2_8X, &clk_name); ++ clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, ++ parent, ++ CLK_SET_RATE_PARENT, ++ 2, 1); ++ WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X])); ++ ++ clk_data->clks = clks; ++ clk_data->clk_num = SUN4I_PLL2_OUTPUTS; ++ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ return; ++ ++err_free_multiplier: ++ kfree(mult); ++err_free_gate: ++ kfree(gate); ++err_unregister_prediv: ++ clk_unregister_divider(prediv_clk); ++err_free_array: ++ kfree(clks); ++err_free_data: ++ kfree(clk_data); ++err_unmap: ++ iounmap(reg); ++} ++CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup); +diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h +new file mode 100644 +index 0000000..071c811 +--- /dev/null ++++ b/include/dt-bindings/clock/sun4i-a10-pll2.h +@@ -0,0 +1,53 @@ ++/* ++ * Copyright 2015 Maxime Ripard ++ * ++ * Maxime Ripard <maxime.ripard@free-electrons.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ ++#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ ++ ++#define SUN4I_A10_PLL2_1X 0 ++#define SUN4I_A10_PLL2_2X 1 ++#define SUN4I_A10_PLL2_4X 2 ++#define SUN4I_A10_PLL2_8X 3 ++ ++#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0006-clk-sunxi-pll2-Add-A13-support.patch b/kernels/linux-libre-lts-knock/0006-clk-sunxi-pll2-Add-A13-support.patch new file mode 100644 index 000000000..e8c807c25 --- /dev/null +++ b/kernels/linux-libre-lts-knock/0006-clk-sunxi-pll2-Add-A13-support.patch @@ -0,0 +1,89 @@ +From eb662f854710e6a438789a4b0d1d0cce8c12379d Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Mon, 21 Sep 2015 13:32:43 +0200 +Subject: [PATCH 6/9] clk: sunxi: pll2: Add A13 support + +The A13, unlike the A10 and A20, doesn't use a pass-through exception for +the 0 value in the pre and post dividers, but increments all the values +written in the register by one. + +Add an exception for both these cases to handle them nicely. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Reviewed-by: Chen-Yu Tsai <wens@csie.org> +--- + drivers/clk/sunxi/clk-a10-pll2.c | 38 +++++++++++++++++++++++++++++++++----- + 1 file changed, 33 insertions(+), 5 deletions(-) + +diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c +index a57742a..5484c31 100644 +--- a/drivers/clk/sunxi/clk-a10-pll2.c ++++ b/drivers/clk/sunxi/clk-a10-pll2.c +@@ -41,9 +41,15 @@ + + #define SUN4I_PLL2_OUTPUTS 4 + ++struct sun4i_pll2_data { ++ u32 post_div_offset; ++ u32 pre_div_flags; ++}; ++ + static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); + +-static void __init sun4i_pll2_setup(struct device_node *node) ++static void __init sun4i_pll2_setup(struct device_node *node, ++ struct sun4i_pll2_data *data) + { + const char *clk_name = node->name, *parent; + struct clk **clks, *base_clk, *prediv_clk; +@@ -70,8 +76,7 @@ static void __init sun4i_pll2_setup(struct device_node *node) + parent, 0, reg, + SUN4I_PLL2_PRE_DIV_SHIFT, + SUN4I_PLL2_PRE_DIV_WIDTH, +- CLK_DIVIDER_ONE_BASED | +- CLK_DIVIDER_ALLOW_ZERO, ++ data->pre_div_flags, + &sun4i_a10_pll2_lock); + if (!prediv_clk) { + pr_err("Couldn't register the prediv clock\n"); +@@ -122,7 +127,7 @@ static void __init sun4i_pll2_setup(struct device_node *node) + */ + val = readl(reg); + val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); +- val |= SUN4I_PLL2_POST_DIV_VALUE << SUN4I_PLL2_POST_DIV_SHIFT; ++ val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; + writel(val, reg); + + of_property_read_string_index(node, "clock-output-names", +@@ -185,4 +190,27 @@ err_free_data: + err_unmap: + iounmap(reg); + } +-CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-pll2-clk", sun4i_pll2_setup); ++ ++static struct sun4i_pll2_data sun4i_a10_pll2_data = { ++ .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, ++}; ++ ++static void __init sun4i_a10_pll2_setup(struct device_node *node) ++{ ++ sun4i_pll2_setup(node, &sun4i_a10_pll2_data); ++} ++ ++CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", ++ sun4i_a10_pll2_setup); ++ ++static struct sun4i_pll2_data sun5i_a13_pll2_data = { ++ .post_div_offset = 1, ++}; ++ ++static void __init sun5i_a13_pll2_setup(struct device_node *node) ++{ ++ sun4i_pll2_setup(node, &sun5i_a13_pll2_data); ++} ++ ++CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", ++ sun5i_a13_pll2_setup); +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch b/kernels/linux-libre-lts-knock/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch new file mode 100644 index 000000000..82484923a --- /dev/null +++ b/kernels/linux-libre-lts-knock/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch @@ -0,0 +1,34 @@ +From 5b3abbee42562a7bcdc6b589a3d8f9b5752550ed Mon Sep 17 00:00:00 2001 +From: Hans de Goede <hdegoede@redhat.com> +Date: Tue, 22 Sep 2015 15:36:00 +0200 +Subject: [PATCH 7/9] ARM: dts: axp209: Add usb_power_supply child node to the ax209 node + +Add a node representing the usb power supply part of the axp209 pmic, note +that the usb power supply and the (to be added later) ac power supply will +each have their own child-node, so that they can be separately specified +as power-supply for other nodes using a power-supply property with a +phandle pointing to the right axp209 child-node. + +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/axp209.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi +index 24c935c..051ab3b 100644 +--- a/arch/arm/boot/dts/axp209.dtsi ++++ b/arch/arm/boot/dts/axp209.dtsi +@@ -89,4 +89,9 @@ + regulator-name = "ldo5"; + }; + }; ++ ++ usb_power_supply: usb_power_supply { ++ compatible = "x-powers,axp202-usb-power-supply"; ++ status = "disabled"; ++ }; + }; +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch b/kernels/linux-libre-lts-knock/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch new file mode 100644 index 000000000..fc7418ab2 --- /dev/null +++ b/kernels/linux-libre-lts-knock/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch @@ -0,0 +1,33 @@ +From db30fce1eea58e50ae8b2722704b4f529c394dba Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Wed, 25 Nov 2015 16:39:04 +0100 +Subject: [PATCH 8/9] ARM: sun5i: chip: Add CPU regulator for cpufreq + +The current DT doesn't have a phandle to the CPU regulator in the CPU node, +which disables the CPU voltage scaling entirely. + +Add that phandle. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts +index 530ab28..f6898c6 100644 +--- a/arch/arm/boot/dts/sun5i-r8-chip.dts ++++ b/arch/arm/boot/dts/sun5i-r8-chip.dts +@@ -70,6 +70,10 @@ + status = "okay"; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++}; ++ + &ehci0 { + status = "okay"; + }; +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch b/kernels/linux-libre-lts-knock/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch new file mode 100644 index 000000000..9704d17d6 --- /dev/null +++ b/kernels/linux-libre-lts-knock/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch @@ -0,0 +1,92 @@ +From 59f0ec231f397001801264063db3b6dcc3eef590 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Tue, 1 Dec 2015 12:14:52 +0100 +Subject: [PATCH 9/9] clk: sunxi: pll2: Fix clock running too fast + +Contrary to what the datasheet says, the pre divider doesn't seem to be +incremented by one in the PLL2, but just uses the value from the register, +with 0 being a bypass. + +This fixes the audio playing too fast. + +Since we now have the same pre-divider flags, and the only difference with +the A10 is the post-divider offset, also remove the structure to just pass +the offset as an argument. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support") +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +--- + drivers/clk/sunxi/clk-a10-pll2.c | 23 +++++------------------ + 1 file changed, 5 insertions(+), 18 deletions(-) + +diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c +index 5484c31..0ee1f36 100644 +--- a/drivers/clk/sunxi/clk-a10-pll2.c ++++ b/drivers/clk/sunxi/clk-a10-pll2.c +@@ -41,15 +41,10 @@ + + #define SUN4I_PLL2_OUTPUTS 4 + +-struct sun4i_pll2_data { +- u32 post_div_offset; +- u32 pre_div_flags; +-}; +- + static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); + + static void __init sun4i_pll2_setup(struct device_node *node, +- struct sun4i_pll2_data *data) ++ int post_div_offset) + { + const char *clk_name = node->name, *parent; + struct clk **clks, *base_clk, *prediv_clk; +@@ -76,7 +71,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, + parent, 0, reg, + SUN4I_PLL2_PRE_DIV_SHIFT, + SUN4I_PLL2_PRE_DIV_WIDTH, +- data->pre_div_flags, ++ CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &sun4i_a10_pll2_lock); + if (!prediv_clk) { + pr_err("Couldn't register the prediv clock\n"); +@@ -127,7 +122,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, + */ + val = readl(reg); + val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); +- val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; ++ val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; + writel(val, reg); + + of_property_read_string_index(node, "clock-output-names", +@@ -191,25 +186,17 @@ err_unmap: + iounmap(reg); + } + +-static struct sun4i_pll2_data sun4i_a10_pll2_data = { +- .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, +-}; +- + static void __init sun4i_a10_pll2_setup(struct device_node *node) + { +- sun4i_pll2_setup(node, &sun4i_a10_pll2_data); ++ sun4i_pll2_setup(node, 0); + } + + CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", + sun4i_a10_pll2_setup); + +-static struct sun4i_pll2_data sun5i_a13_pll2_data = { +- .post_div_offset = 1, +-}; +- + static void __init sun5i_a13_pll2_setup(struct device_node *node) + { +- sun4i_pll2_setup(node, &sun5i_a13_pll2_data); ++ sun4i_pll2_setup(node, 1); + } + + CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", +-- +cgit v0.12 + diff --git a/kernels/linux-libre-lts-knock/PKGBUILD b/kernels/linux-libre-lts-knock/PKGBUILD index 2abfb7aae..f71717338 100644 --- a/kernels/linux-libre-lts-knock/PKGBUILD +++ b/kernels/linux-libre-lts-knock/PKGBUILD @@ -57,7 +57,13 @@ source=("http://linux-libre.fsfla.org/pub/linux-libre/releases/${_pkgbasever}/li "https://repo.parabola.nu/other/rcn-libre/patches/${_pkgver%-*}/rcn-libre-${_pkgver%-*}-${rcnrel}.patch.sig" '0001-ARM-sunxi-Add-R8-support.patch' '0002-ARM-sun5i-Add-CHIP-DTS.patch' - '0003-ARM-sun5i-Add-R8-DTSI.patch' + '0003-ARM-sun5i-chip-Enable-the-audio-codec.patch' + '0004-ARM-sun5i-Add-R8-DTSI.patch' + '0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch' + '0006-clk-sunxi-pll2-Add-A13-support.patch' + '0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch' + '0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch' + '0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch' '0001-ARM-atags-add-support-for-Marvell-s-u-boot.patch' '0002-ARM-atags-fdt-retrieve-MAC-addresses-from-Marvell-bo.patch' '0003-SMILE-Plug-device-tree-file.patch' @@ -90,7 +96,10 @@ sha256sums=('48b2e5ea077d0a0bdcb205e67178e8eb5b2867db3b2364b701dbc801d9755324' 'SKIP' 'c30f5b73d31202d1453c15eafc933a374a9087169761cd8d9404a80591ddabb2' '69517e7f99bfbb8f4483162a1e76bda7f6845284476c20dbd16e074249400396' - '1970e32e3dc9da22c79c6ef9fe22dd4874a76a81ed1012ddfc7e83d1a2a0214b' + '576d0be8df3450f3a6db8ea5aba6ebda1a3417d212763a403c4df0c333ef2a9d' + 'a359eacdb88f050b9d8b6eee9e84c7b50215ca804dbc0c2f79c2f80c7fae1b86' + '0621cdfa195494509c6f8d328932c0ff3523a289880c378d7c46e93ca2e6cce4' + 'f1294da7523cbe1fb6b0ef3cb054548d8589c6e3dd64af7b8cf18a7845b68459' '203b07cc241f2374d1e18583fc9940cc69da134f992bff65a8b376c717aa7ea7' '28fb8c937c2a0dc824ea755efba26ac5a4555f9a97d79f4e31f24b23c5eae59c' '39bfd7f6e2df0b87b52488462edb2fbcfaf9e3eb2a974fc7b3bc22147352fece' @@ -134,7 +143,13 @@ prepare() { # Parabola patches patch -p1 -i "${srcdir}/0001-ARM-sunxi-Add-R8-support.patch" patch -p1 -i "${srcdir}/0002-ARM-sun5i-Add-CHIP-DTS.patch" - patch -p1 -i "${srcdir}/0003-ARM-sun5i-Add-R8-DTSI.patch" + patch -p1 -i "${srcdir}/0003-ARM-sun5i-chip-Enable-the-audio-codec.patch" + patch -p1 -i "${srcdir}/0004-ARM-sun5i-Add-R8-DTSI.patch" + patch -p1 -i "${srcdir}/0005-clk-sunxi-Add-a-driver-for-the-PLL2.patch" + patch -p1 -i "${srcdir}/0006-clk-sunxi-pll2-Add-A13-support.patch" + patch -p1 -i "${srcdir}/0007-ARM-dts-axp209-Add-usb_power_supply-child-node-to-the-ax209-node.patch" + patch -p1 -i "${srcdir}/0008-ARM-sun5i-chip-Add-CPU-regulator-for-cpufreq.patch" + patch -p1 -i "${srcdir}/0009-clk-sunxi-pll2-Fix-clock-running-too-fast.patch" # ALARM patches patch -p1 -i "${srcdir}/0001-ARM-atags-add-support-for-Marvell-s-u-boot.patch" |