From 7efdc721db9220642778a1183ec24ee2762b8ee8 Mon Sep 17 00:00:00 2001 From: "Luke T. Shumaker" Date: Sun, 13 Oct 2024 21:22:45 -0600 Subject: wip w5500 --- cmd/sbc_harness/hw/spi.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 cmd/sbc_harness/hw/spi.h (limited to 'cmd/sbc_harness/hw/spi.h') diff --git a/cmd/sbc_harness/hw/spi.h b/cmd/sbc_harness/hw/spi.h new file mode 100644 index 0000000..4a160ca --- /dev/null +++ b/cmd/sbc_harness/hw/spi.h @@ -0,0 +1,44 @@ +#ifndef _HW_SPI_H_ +#define _HW_SPI_H_ + +#include /* for size_t */ + +enum spi_mode { + SPI_MODE_0 = 0, /* clk_polarity=0 (idle low), clk_phase=0 (sample on rise) */ + SPI_MODE_1 = 1, /* clk_polarity=0 (idle low), clk_phase=1 (sample on fall) */ + SPI_MODE_2 = 2, /* clk_polarity=1 (idle high), clk_phase=0 (sample on rise) */ + SPI_MODE_3 = 3, /* clk_polarity=1 (idle high), clk_phase=1 (sample on fall) */ +}; + +struct bidi_iovec { + void *iov_read_dst; + void *iov_write_src; + size_t iov_len; +}; + +struct spi; + +/* This API assumes that an SPI frame is a multiple of 8-bits. + * + * It is my understanding that this is a common constraint of SPI + * hardware, and that the RP2040 is somewhat unusual in that it allows + * frames of any length 4-16 bits (we disconnect the CS pin from the + * PL022 SSP and manually GPIO it from the CPU in order to achieve + * longer frames). + * + * But, more relevantly: The W5500's protocol uses frames that are 4-N + * octets; so we have no need for an API that allows a + * non-multiple-of-8 number of bits. + */ +struct spi_vtable { + void (*readwritev)(struct spi *, const struct bidi_iovec *iov, int iovcnt) +}; + +struct spi { + struct spi_vtable *vtable; + + /* This is where your implementation data goes. */ + char data[0]; +}; + +#endif /* _HW_SPI_H_ */ -- cgit v1.2.3-2-g168b