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authorFrank Wuerthwein <fkw@ucsd.edu>2009-03-18 13:00:44 +0000
committerFrank Wuerthwein <fkw@ucsd.edu>2009-03-18 13:00:44 +0000
commitc2c029003b7d5e2e024543bafc69725608ae5e9e (patch)
tree3acb6c616799b2f64586997959d07e9a124f5926 /doc/lib/rrdFlotSupport_js.html
parent3d31ceb2029dc34f327023f4d35d7e7b048805a1 (diff)
Document want_rounding
Diffstat (limited to 'doc/lib/rrdFlotSupport_js.html')
-rw-r--r--doc/lib/rrdFlotSupport_js.html16
1 files changed, 16 insertions, 0 deletions
diff --git a/doc/lib/rrdFlotSupport_js.html b/doc/lib/rrdFlotSupport_js.html
index 0173e8b..554caec 100644
--- a/doc/lib/rrdFlotSupport_js.html
+++ b/doc/lib/rrdFlotSupport_js.html
@@ -91,6 +91,14 @@ Input parameters:
<P>Index of the desired RRA.</P>
</TD>
</TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=20%>
+ <P>want_rounding</P>
+ </TD>
+ <TD WIDTH=80%>
+ <P>If not false, all timestamps will be truncated to the RRA step.</P>
+ </TD>
+ </TR>
</TBODY>
</TABLE>
</DIV>
@@ -205,6 +213,14 @@ Input parameters:
(If false, only the order distinguishes the requested DSs)</P>
</TD>
</TR>
+ <TR VALIGN=TOP>
+ <TD WIDTH=20%>
+ <P>want_rounding</P>
+ </TD>
+ <TD WIDTH=80%>
+ <P>If not false, all timestamps will be truncated to the RRA step.</P>
+ </TD>
+ </TR>
</TBODY>
</TABLE>
</DIV>